An inverter circuit for driving a load such as a motor is a converter for switching a direct current and an alternating current. Thus, the converter converts a direct voltage to an alternating voltage so that the inverter circuit supplies electricity to the load. The inverter circuit for driving an inductive type motor includes an IGBT (i.e., insulated gate bipolar transistor) and a FWD (i.e., free wheel diode). The IGBT provide s switching device. The FWD bypasses the current flowing through the motor when the IGBT turns off so that the FWD controls the current flowing through the motor to be constant against switching operation of the IGBT. Specifically, the IGBT electrically coupled between a direct current supply and the motor so that a predetermined voltage is applied to the motor. When the IGBT turns off, the current flowing through the motor flows back to the direct current supply through the FWD because of energy accumulated in a reactance L of the motor. Thus, an inverse direct voltage is applied to the motor. Thus, the switching operating of the IGBT provides to energize the alternating voltage from the direct current supply without rapidly shutting the current flowing through the motor. Since the inverter circuit provides these operations, it is necessary to provide the FWD inversely connecting in parallel to the IGBT. Thus, a pair of the FWD and the IGBT is formed, so that the IGBT and the FWD are inversely connected each other in series.
FIG. 8 shows an example of a semiconductor device 90 as a comparison of the present disclosure. The device is used for an inverter circuit to drive a load such as a motor. The device includes an IGBT cell and a diode cell, which are formed in a same semiconductor substrate. FIG. 9 shows an equivalent circuit of the device 90 in FIG. 8.
The device 90 includes a N− conductive type semiconductor substrate 1 having a principal surface. A P conductive type layer 2 is formed in a surface portion of the substrate 1 on the principal surface side. A principal surface side N conductive type region 3 (i.e., principal N region) having a high impurity concentration and a principal surface side high impurity concentration P conductive type region 4 (i.e., principal P region) having a high impurity concentration are formed in a surface portion of the P conductive type layer 2. Further, a backside P conductive type region 5 (i.e., backside P region) having a high impurity concentration and a backside N conductive type region 6 (i.e., backside N region) having a high impurity concentration are formed in a surface portion of the substrate 1 on the backside.
A trench T1 is formed in the device 90. The trench T1 penetrates the principal surface side N conductive type region 3 and the P conductive type layer 2, and reaches the N− conductive type semiconductor substrate 1.
A first electrode layer 8 made of poly silicon is disposed in the trench T1 through an insulation film 7, which is formed on an inner wall of the trench T1. The first electrode layer 8 provides a gate electrode of the IGBT cell 90i. A second electrode layer 10 made of aluminum is formed on the principal surface of the substrate 1 through an interlayer insulation film 9. The second electrode layer 10 is electrically connected to the P conductive type layer 2 through the principal surface side N conductive type region 3 and the principal surface side high impurity concentration P conductive type region 4. The second electrode layer 10 provides an anode electrode of the diode cell 90d and the emitter electrode of the IGBT cell 90i. A third electrode layer 11 is formed on the backside of the substrate 1, and electrically connected to the backside P conductive type region 5 and the backside N region 6. The third electrode layer 11 provides the collector electrode of the IGBT cell 90i and the cathode electrode of the diode cell 90d. 
Thus, in the device 90, the principal N region 3 provides the emitter region of the IGBT cell 90i, the P conductive type layer 2 provides the channel layer of the IGBT cell 90i, and the backside P region 5 provides the collector region of the IGBT cell 90i. Further, the boundary between the substrate 1 and the P conductive type layer 2 provides a PN junction of the diode cell 90d, the principal P region 4 provides the anode region of the diode cell 90d, and the backside N region 6 provides the cathode region of the diode cell 90d. As shown in FIG. 9, in the device 90, the IGBT cell 90i and the diode cell 90d are electrically connected in parallel to each other.
When the diode 90d in the device 90 is used as the FWD in the inverter circuit, a current waveform is important when the diode is inversely recovered in a case where the diode switches from an on-state to an off-state.
FIG. 10A shows an evaluation circuit for measuring the current waveform of the current flowing through the diode 90d. FIG. 10B is a sample of the current waveform.
Two semiconductor devices 90a, 90b have the same structure as the device 90 shown in FIG. 8. The IGBT cell 90ai in the first device 90a provides a switching device, and the current Id flowing through the diode cell 90bd in the second device 90b is detected when the IGBT in the second device 90b short-circuits.
As shown in FIG. 10B, when the IGBT 90ai in the first device 90a turns off, a circulation current Iif flows in the diode 90bd of the second device 90b. When the IGBT cell 90ai of the first device 90a turns on, a reverse current instantaneously flows in the diode 90bd pf the second device 90b. The reverse current flowing in an opposite direction to the circulation current Iif has a peak current, which is defined as a recovery current Irr. In case of reverse recovery, the power supply voltage is applied to the diode, and a product of the voltage by the current is defined as a recovery loss. In general, it is required for a rectifier diode to have a small recovery current Irr, a small recovery loss in case of a reverse recovery process, and soft recovery of the current in case of the reverse recovery process.
In the device 90 shown in FIG. 8, the diode cell 90d functions as a FWD having a PN junction of a boundary between the P conductive type layer 2 and the substrate 1 in the IGBT cell 90i. Thus, the diode cell 90d is formed together with the IGBT cell 90i. The diode cell 90d has a high impurity concentration of the P conductive type layer 2, which corresponds to a P conductive type portion of the FWD. Thus, when the diode cell 90d functions with forward operation, a hole is introduced with high impurity concentration, so that the recovery current Irr becomes larger in case of the recovery operation. Accordingly, recovery performance becomes low.
To improve the recovery performance of the diode cell 90d, it is preferred that a surface pattern, an impurity concentration profile, or a life time in the diode is optimized in case of a single high speed diode. However, since the diode cell 90d is formed together with the IGBT cell 90i, structure change such as the above optimization for improving the diode performance may deteriorate the performance of the IGBT cell 90i. Thus, it is difficult to improve the diode performance.
To improve the diode performance without reducing the performance of the IGBT cell 90i, a semiconductor device is disclosed in JP-A-2005-101514 (corresponding to US Patent Publication No. 2005-0045960).
FIG. 11 shows the semiconductor device 91 in US Patent Publication No. 2005-0045960.
In the device 91, the channel region of the IGBT cell 91i is provided by the P conductive type region 2w, which is formed by diffusing in a horizontal direction. The PN junction of the diode cell 91d is formed between the N conductive type semiconductor substrate 1 and the P conductive type region 2w, which expands in the horizontal direction of the substrate 1. Specifically, the PN junction is disposed at a boundary between an end of the P conductive type region 2 in the horizontal direction and the substrate 1. The end of the P conductive type region 2 in the horizontal direction has a comparative low impurity concentration, so that an introduced hole concentration is reduced in case of a forward operation of the diode cell 91d. Thus, the recovery performance is improved.
The device 91 shown in FIG. 11 includes no principal P region 4, although the device 90 in FIG. 8 includes the principal P region 4. The P conductive type region 2w in the device 91 has a surface impurity concentration, which is lower than that of the P conductive type region 2 in the device 90. In this case, a parasitic PNP transistor has a large base resistance, which is provided by a pinch resistance of the P conductive type channel (i.e., the P conductive type region 2w). Here, the parasitic PNP transistor is composed of the principal N region 3, the P conductive type region 2w and the substrate 1. Thus, current amplification factor of the parasitic NPN transistor becomes larger. In this case, when a high voltage surge is applied to the device 91, and an avalanche current flows in the P conductive type region 2w, the parasitic NPN transistor easily functions so that the device 91 may be broken by the high voltage surge. Accordingly, although the recovery performance of the diode cell 91d is improved, breakdown energy is small so that the device 91 has a small surge withstand voltage.
Thus, it is required for a semiconductor device to have sufficient performance of the IGBT cell and sufficient recovery performance of the diode cell with a sufficient surge withstand voltage.